1. Field of the Invention
The present invention relates generally to a short cycle DRAM using a floating wordline, a dynamic row decoder and bitline VDD precharge, and more particularly pertains to a short cycle DRAM using a floating wordline, a dynamic row decoder and bitline VDD precharge, primarily to reduce the DRAM size.
2. Discussion of the Prior Art
In the historical development of DRAMs, the speed of a DRAM has not been as important as its density. In a processor system, a DRAM is used as the main memory for storing large amounts of back-up data. While SRAMs, due to their high-performance nature, are used mostly for L1 or L2 cache for storing data to be used immediately by the processors. However, as the technology and circuit techniques have improved, the performance of DRAMs now approaches that of SRAMs. On the other hand, the density of SRAMs still cannot compete with that of DRAMs. As a result, there have been more recent proposals for high performance DRAM designs aimed at markets for SRAM replacement, for example, one-transistor SRAM, cache DRAM and short cycle DRAM, DRAM cores with RAMBUS interface protocol, etc.
A short cycle DRAM proposed by Kirihata, et al. (IBM docket FIS920000411) was claimed to be able to achieve a cycle time of 3.3 ns using today 0.17 um technology. Key elements to accomplish such high performance include, (1) small array size and thus less loading on wordlines, bitlines and datalines, (2) destructive read/write, therefore, no write-back period is required within each cycle, (3) A small dual-port SRAM cache is used to schedule pipelined caching activities, and (4) very wide data I/O for high data rate embedded applications. This short cycle DRAM does not support page mode operation.
For designing a short cycle DRAM, one critical concern is how to keep the array efficiency (i.e. ratio of array area over total chip area) high, so that the density is still much higher than that of a SRAM. Due to a small array architecture, the array efficiency of a short cycle DRAM is much lower than that of a conventional DRAM. For example, each wordline of a short cycle DRAM drives only 128 pairs of bitlines.
FIG. 1 is a comparison of wordline driver and wordline length for the present invention and the prior art. FIG. 1A illustrates the present invention wherein a master wordline MW/L drives 4 sets of local wordlines LW/Ls, each of which has 32 bitline pairs, for a total of 128 pairs of bitlines. For a conventional high-density DRAM, as shown in FIG. 1B, each wordline may drive up to 2048 pairs of bitlines, or 16 times more. Therefore, it is important to significantly reduce the size of support devices, such as wordline drivers, sense amplifiers, etc., in order for a short-cycle DRAM to be attractive in the high-performance RAM market.
FIG. 2A-1 illustrates a typical prior art wordline driver of a conventional DRAM which comprises a level shifter L/S and a driver D. The level shifter converts the input address voltage from ground/Vint, to Vwl/Vpp (or negative wordline voltagexe2x88x920.5V/boost wordline voltage, e.g. 2.0V). However, this approach suffers a high dielectric stress problem. For example, the worst switching stress on the pMOS pull-up device PU is in the range of Vpp to a negative level.
To reduce such a stress, in the prior art circuit of FIG. 2A-2 two level shifters L/S, L/Sa are used. In the circuit of FIG. 2A-1 and other circuits herein, as is conventional in the art, pMOS devices are illustrated with a small circle at the gate thereof and nMOS devices are illustrated without such a small circle. The switching stress is now reduced to Vpp-ground on the pMOS pull-up device PU of the wordline driver. Similarly, the other level shifter L/Sa reduces the switching stress on the gate oxide of the pull-down nMOS device PD. The output from the first level shifter L/S is coupled to the gate of a pull-up pMOS PU. The output from the second level shifter L/Sa is coupled to the gate of a pull-down nMOS PD of the wordline driver. The wordline driver D consists of a pull-up pMOS PU, a pull-down MOS PD, and a second nMOS pull-down devices K which is called a killer device. This killer device is used to deselect the half-selected wordlines so they will not be floating. Details are further explained in a following section.
The wordline drivers are decoded in a group of four, D1, D2, D3, D4 and D5, D6, D7, D8 as shown in FIG. 3A. That is, each decoded output from a level shifter is tied to a group of four wordline drivers. One of the four wordline drivers is selected by decoding the sources of the pull-up pMOS devices as well as the gates of the killer devices.
For example, as shown in FIG. 3A, if the first wordline WL1 is selected, the first group of four wordline drivers D1, D2, D3, D4 is first selected through the first level shifter by switching its output which couples the gates of the pMOS pull-up devices from Vpp to ground, and through the second level shifter by switching its output which couples the gates of the pull-down nMOS devices from Vint to Vwl. At this moment, the first group of the four wordline drivers are ready for the second level decoding to select one of the four wordlines. A two-bit predecoder (not shown in FIG. 3A) is used to activate one of the four wordline drivers. In order to activate WL1, the source of the pMOS pull-up device is tied to Vpp, while the gate of the killer device is tied to Vwl, as shown in FIG. 3A. At this moment, the sources of the other three pMOS pull-up devices stay at ground, and the gates of the other three killer devices stay at vint, as shown in FIG. 3A. This second level decoding is applied to all the wordline drivers in the first level decoded group of four. As shown in the bottom of FIG. 3A, for drivers D5-D8, the gates of all the drivers are deselected, that is, Vpp is tied to the pMOS pull-up devices and Vint is tied to the nMOS pull-down devices.
The killer devices K play an important role to hold the half-selected wordlines at Vwl to avoid a wordline floating problem. For example, as illustrated in FIG. 3A, the half-selected wordlines are those wordlines WL2-WL4 which are not selected by the second level decoding but are selected by the first level decoding. For example, the drivers of WL2, WL3 and WL4 are half-selected. Since the gates of the pull-down nMOS devices are turned off by being connected to Vwl, without killer devices, these wordlines would float.
For a prolonged wordline operation, such as a page mode operation, the coupling effect could cause a data loss on these wordlines. Therefore, it is desirable that during array operation no wordlines float. On the other hand, for a small array architecture, each time all of the cells along a wordline are accessed, no page mode operation is needed. As a result, floating wordlines may be acceptable because they only float for a short period of time. A description of a new wordline driver circuit follows which significantly reduces the driver size without compromising the wordline access performance.
Accordingly, it is a primary object of the present invention to provide a short cycle DRAM using a floating wordline, dynamic row decoder and bitline VDD precharge which improves the array efficiency of a short cycle DRAM (3-6 ns) without compromising its performance. More specifically, the subject invention provides a small size wordline driver circuit to reduce row size of a short cycle DRAM without compromising row access timing.
A further object of the present invention is to implement a dynamic decoding operation which intentionally allows some of the deselected wordlines to float during row access.
One more object of the subject invention is to implement a Vdd bitline precharge/sensing technique to avoid a detrimental (or positive) coupling effect to the floating wordlines during row accessing.
Another object of the present invention is to implement a Vdd data-line (or DQ) precharge for a read operation and control of incoming data timing to avoid a detrimental (or positive) coupling effect for a write operation.